Hossam Mousa

Four antennas on a chip. Some 150 chips on a board. And that’s before you configure the beam. Ku band today, Ka tomorrow. Principal ASIC Design Engineer Hossam Mousa explores five of the big challenges ahead as we scale up and get to work on our next generation chip.

A new smartphone has at least eight antennas. Our Active Electronically Steered Arrays (AESAs) have 3,600.

‘And they love to talk to each other,’ says RF/Analog expert Hossam Mousa who joined Hanwha Phasor from Huawei. ‘So, the first challenge we face is to how to prevent that chatter from impacting our system. It’s the world’s first commercial AESA for satcom on the move, so there’s a lot to learn.’

For ASIC engineers working at design houses or at the 5G and satcom giants, the product as a whole isn’t part of the picture. You get a brief for the chip and you’re told to get on with it. But here, it’s about how you combine narrow-focus expertise with big-picture thinking to optimise the system. The Hanwha Phasor lab in London is building and testing prototypes so engineers get regular feedback on how their work impacts the integrated product.

So, what are the five challenges ahead?

1. Think nano, micro and macro, at the same time

“You get a bigger horizon here,’ says Mousa, ‘so you can make more informed choices. But as the system parameters get tighter, you have to be more creative than ever. And that’s what appeals to me: ASIC design is an art not a science, after all.”

For Hanwha Phasor ASIC experts, the first big challenge starts at the smallest scale.

“I used to find it hard to place two antennas on a chip,” smiles Mousa. “With eight, it’s a whole other level. And that’s what makes it so much fun.” Beyond the physical location of the antenna, there are huge questions concerning transceiver architecture to answer. Then there are power levels to optimise, guaranteeing that any coupling between the antenna is under the noise level required by the system as a whole.

2. In between the chips is just as important as inside them

The second challenge is the relationship between the chips. Do you synchronize the phase of the local high frequency oscillator and calibrate them or do you go with a phased locked loop solution? As with many aspects of ASIC design, there are pros and cons to each approach. Establishing the best solution needs robust thinking and close collaboration.

The same is true for challenge number three: configuration of the beam form itself.

3. The world is analog—isn’t it?

Over the coming months, the team will run a range of complex mathematical models to establish the best way ahead. As satcom is still an open field, there are many options: some competitors rely on a beam-forming solution in the analog domain, others on a digital one, and still others a combination of the two.

“None of the answers are in the textbooks,” says Mousa. “So, we need brilliant ASIC engineers from different fields. Seasoned engineers who can still shine their light equally in all directions, like stars. If they can really challenge us, they’ll really challenge themselves. Win, win.”