Principal Design Engineer
Palma Ceia SemiDesign
Huawei Technologies Research & Development
2016 – 2019
2013 – 2016
2007 – 2013
2004 – 2007
Master’s degree in electronics from Ain Shams University, Egypt
Four antennas on a chip. Some 150 chips on a board. And that’s before you configure the beam. Ku band today, Ka tomorrow. Principal ASIC Design Engineer Hossam Mousa explores five of the big challenges ahead as we scale up and get to work on our next generation chip.
A new smartphone has at least eight antennas. Our Active Electronically Steered Arrays (AESAs) have 3,600.
‘And they love to talk to each other,’ says RF/Analog expert Hossam Mousa who joined Hanwha Phasor from Huawei. ‘So, the first challenge we face is to how to prevent that chatter from impacting our system. It’s the world’s first commercial AESA for satcom on the move, so there’s a lot to learn.’
For ASIC engineers working at design houses or at the 5G and satcom giants, the product as a whole isn’t part of the picture. You get a brief for the chip and you’re told to get on with it. But here, it’s about how you combine narrow-focus expertise with big-picture thinking to optimise the system. The Hanwha Phasor lab in London is building and testing prototypes so engineers get regular feedback on how their work impacts the integrated product.
So, what are the five challenges ahead?
“You get a bigger horizon here,’ says Mousa, ‘so you can make more informed choices. But as the system parameters get tighter, you have to be more creative than ever. And that’s what appeals to me: ASIC design is an art not a science, after all.”
For Hanwha Phasor ASIC experts, the first big challenge starts at the smallest scale.
“I used to find it hard to place two antennas on a chip,” smiles Mousa. “With eight, it’s a whole other level. And that’s what makes it so much fun.” Beyond the physical location of the antenna, there are huge questions concerning transceiver architecture to answer. Then there are power levels to optimise, guaranteeing that any coupling between the antenna is under the noise level required by the system as a whole.
The second challenge is the relationship between the chips. Do you synchronize the phase of the local high frequency oscillator and calibrate them or do you go with a phased locked loop solution? As with many aspects of ASIC design, there are pros and cons to each approach. Establishing the best solution needs robust thinking and close collaboration.
The same is true for challenge number three: configuration of the beam form itself.
Over the coming months, the team will run a range of complex mathematical models to establish the best way ahead. As satcom is still an open field, there are many options: some competitors rely on a beam-forming solution in the analog domain, others on a digital one, and still others a combination of the two.
“None of the answers are in the textbooks,” says Mousa. “So, we need brilliant ASIC engineers from different fields. Seasoned engineers who can still shine their light equally in all directions, like stars. If they can really challenge us, they’ll really challenge themselves. Win, win.”
Once that has been fully explored and a way forward agreed, the fourth challenge will be to implement the circuits and integrate them with the rest of the system, collaborating with experts in all key functions: hardware, software, mechanical engineering, systems integration, test, validation and characterisation.
“Fortunately, we have a very open, supportive culture here,” says Mousa. “We have very talented men and women from all over the world and that helps to keep our perspectives open. At the same time, we’re still relatively small: we can get the job done because we know who to talk to and we can get hold of them fast.”
To date, younger ASIC engineers have joined as PhDs from leading universities. Experienced hires come from established leaders in wireless, SERDES and optical transceivers. One of our engineers joined from Texas Instruments. Another turned down an offer from one of the Taiwanese fabless semiconductor leaders to join us, deciding that the opportunities on offer at a well-funded, fast-growth ‘scale-up’ were bigger, brighter and more challenging.
Being part of a bigger, ambitious enterprise also has its benefits. Hanwha Phasor’s parent company, Hanwha Systems, sees AESA expertise as a critical success factor in its planned LEO satellite constellation. At each stage, we have to make sure enterprise customers have the choices they demand. So, the fifth challenge is to develop a Ka terminal aero stream in addition to our Ku offering.
“I’m really excited about this,” grins Hossam. “Adding microwave to the mix brings a wonderful new set of challenges to the electrical focus we have with Ku.”
Opportunities include EM modelling and simulation, exploring new combinations of theories as well as next-generation tools beyond Cadence.
“In some ways, it’ll be like going back to academic life,” says Mousa. “We get the fun of studying and working in different fields. After many years of intense focus, it’s so refreshing to broaden your horizons again.”
The best ASIC engineers want a new challenge every two or three years. Hanwha Phasor’s unique combination of secure backing, agile, open culture and big ambition mean they can stay in one place and get what they need to stretch them.
“We want to create a legacy to be proud of,” says Mousa. “So we travel light, we think big and we work hard. That’s what delivers.”